The present invention relates, in general, to embedded metal nanocrystals for improving contact resistance and for enhancing tunneling current through a semiconductor/metal interface, or through a metal/insulator interface, and more particularly to the provision of metal nanocrystals embedded in another metal having a different work function to produce fringing electric fields at an interface with a semiconductor or insulator.
The technology of low-resistance ohmic contacts is crucial to the manufacture of reliable VLSI systems. In conventional ohmic contacts, the reduction of a tunneling barrier (with or without surface Fermi level pinning) at the interface between a metal contact and a semiconductor is achieved by doping the semiconductor near the surface to degenerate levels. However, this technique hinges upon the availability of a reliable, shallow dopant, in the semiconductor, as well as a device structure that permits a high concentration of impurities at its surface.
The former criterion is not met easily for large band gap (e.g., p-type SiC) or organic semiconductors (e.g., MEH-PPV polymer). Furthermore, in device structures such as ultra-thin body silicide source/drain MOSFETs, which have been proposed as alternatives to the conventional MOSFET at nanometer gate lengths, the source-channel contact resistance in the ON state of the device is a significant problem. In these latter cases, the device structure does not allow the use of increased dopant concentration as a means to reduce the tunneling barrier width, since one of the prime advantages of these devices lies in the realization that they could eliminate the necessity of doping in CMOS technology altogether. It is, therefore, important to develop new schemes that can provide low resistance contacts even at modest doping levels, or can provide contacts which are totally doping independent.
Briefly, in accordance with the present invention, a novel contact is provided in which a metal/semiconductor or a metal/insulator contact resistance is reduced by more than 100 times over previously-available contact schemes. As described in detail below, the improved (reduced) contact resistance is obtained by forming, at a metal/semiconductor or a metal/insulator contact location, metal nanocrystals embedded in the metal contact layer. The nanocrystals and the metal contact layer have different work functions and, therefore, produce a large, built-in electric fringing field at the triple interfaces of the nanocrystals with the metal of the contact layer and the semiconductor or insulator substrate on which the contact is formed. The fringing field, which enhances tunneling through the potential barrier at the metal/semiconductor or metal/insulator interface, originates from the metal/nanocrystal interface and, therefore, is independent of the semiconductor impurity concentration. Furthermore, the dipole charge density in the metal is very high (it is inversely proportional to the Debye length in the metal) and will surpass the interface charge states within the metal-semiconductor interface.
The technique for forming the low resistance contact can be applied to large band gap semiconductors, but is also employed in low temperature TFTs, electronics on organic substrates, MEMS switches, and the like. When combined with a thin-body silicon-on-insulator (SOI) Schottky barrier MOSFET to reduce the ON state contact resistance, this contact scheme may be used to take MOSFET scaling to the 20 nm regime.
The low-resistance contact of the present invention may be fabricated, for example, by evaporating or sputtering on a clean, smooth Si (100) substrate surface a wetting layer of metal with an initial thickness ranging from 1-5 nm. This is done after a dilute HF etch of the surface. Thereafter, a rapid thermal annealing (RTA), ranging from 5 seconds to 2 minutes with a peak temperature near its bulk eutectic temperature with silicon, is performed in an inert ambient atmosphere. For certain metals, with proper selection of the annealing profile, nanocrystals are formed in the wetting layer at the silicon substrate surface (see, for example, Suo, et al, Physics Review 1998, B58, pps. 5116-5120). If a desired wetting layer metal does not self-assemble into the desired pattern of scattered, spaced, individual crystals of various diameters on the semiconductor substrate, then the desired crystal shapes can be obtained by using a pattern transfer from self-assembled anodic alumina nanohole arrays, or can simply be obtained by nano-lithography. After the nanocrystals are formed, a thick layer of contact (or cap) metal, around 0.5 to 1 xcexcm, for example, with a different work function than that of the metal which was used for the nanocrystals, is evaporated or sputtered on the substrate surface without any significant substrate heating.
The basic embedded nanocrystal process described above is integrated with standard UV lithography steps to make contact resistance structures in which the work function difference between the nanocrystals and the contact metal sets up a large electric field which extends into the silicon substrate, close to the triple interface of the device. This triple interface is located where the contact metal, the nanocrystals and the semiconductor come together. The field is very similar to the fringing field between two capacitor plates. Because the materials retain their individual electrical properties in the nanoscale, the resulting electric field can be significantly higher than that produced in the original metal-silicon Schottky fields. There is, therefore, an electric field contour near the triple interface, in which the resulting potential barrier is significantly thinner than normal, thus enhancing field emission.
It is noted that in the foregoing process, the transport of metal atoms on the silicon surface is limited by temperature-dependent surface mobility, and growth is limited to the activated reaction/nucleation sites. The shape, size and spacing of the nanocrystals have dependence on wetting-layer thicknesses and their RTA profiles, as is the case for metal on silicon dioxide.
There are two competing processes during the RTA annealing step. The first is nanocrystal formation by minimization of the surface energy and the second is silicide formation by the metal-silicon reaction. Which process dominates depends on their relative rates. For materials like Ti, that can form silicides at temperatures much lower than their eutectic temperatures with silicon, a thin film of silicide is formed on annealing. This silicide film is less likely to form nanocrystals subsequently because of the gradual change in stiochiometry along the thickness of the film, which results in excellent adhesion to silicon. For other materials such as Au and Ag, however, the formation of nanocrystals is favored over the silicidation. Because the nanocrystal formation involves minimization of local total energy, metal diffusion and sintering into the silicon substrate is much less likely to happen.
The tunneling enhancement effect of the present invention is much larger in metal/insulator interfaces than in metal semiconductor interfaces, due to the larger barrier height normally encountered at insulator interfaces. The formation of metal nanocrystals on an insulator such as silicon oxide allows the nanocrystals to be used as floating gates instead of control gates. The work function difference between the nanocrystal and the contact, or cap, metal sets up a large electric field in the oxide close to the triple interface. As discussed above, a large density of dipole charges can be formed at the interface between two metals to produce a contour near the triple interface in which the potential barrier is significantly thinner than normal. The charge separation dies down over a few atomic lengths and the peak electric field also dies down relatively faster than the Debye length in the oxide. This is the ideal asymmetric situation for application of the invention to an EEPROM, since forward injection in such a device is much more enhanced, while backward leakage is not seriously affected at the barrier. This application to EEPROM devices resolves the requirement for high erase voltages in these devices, making EEPROM cells much more compatible with other CMOS device operations and provides easier technology scaling.